Basic design

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Sinclair SIF is dual channel serial interface. Device is based on two 16C650 Uarts with 7,3738MHz clock. By internal Baud rate generator is possible set speed from 50Baud to 460800Baud. SIF is completely powered by 3,3Volts by internal linear regulator, but all inputs are 5Volts tolerant.

Addressing:

Interface needs 8 I/O ports and works with full 8 bits port addressing, base address is selectable by solder jumpers on board. Address range is follow:

Addressing2Addressing2

Hardware:

Hardware model can be easier understand by follow picture:
schemaschema
Main logic is in CPLD which take care about addressing and INT generating. All communication, FIFO and Baud rate generating is done by 16C650 UARTs.
Data and selection one of UARTS is controlled by CPLD (signals CS1 and CS2).
Channel 1 is in basic configuration connected to TTL – RS232 converter but this wires could be used for 3.3V TTL devices connected to pin header at board.
Channel 2 is internally multiplexed (by 74HC157) to two TTL channels. First go to location for ConnectOne modules (Wifi or Ethernet) a second go to IrDA optional module. This multiplexer on channel 2 is controlled by general purpose IO2 on Uart2.

Interrupt

Interrupt is also controlled by CPLD and is managed in two levels. First level is interrupt generated by UARTS (signals UART1I and UART2I) this signals can be active in certain situations (Full RX FIFO, Empty TX FIFO, RTS, etc) and in this level goes only to CPLD Control register.
Second level is INT signal for CPU. This signal is bidirectional and works in two automatic switching modes. When Interrupt from SIF is enabled (INTE bit) it is open collector output and is in 0 when any of UART1I or UART2I is active. Signals stays active till IM2 vector is read out (INT Ack) or M1 makes 3 cycles. After this is signal released. Second mode is signal input and device is waiting for INT from ULA. This is only active in time from INT Ack to time when we delete UART1I or UART2I flags. Purpose of this monitoring of INT is checking if during SIF IM2 service was not appear ULA INT. This should be checked before leaving SIF IM2 service and if necessary standard INT service could be called.
Addressing1Addressing1

Registers Layout

RegistersRegisters
All registers are same according Datasheet for 16C650 in download center

Only CONFIG register works as follow:

  • CONFIG (R/W, Base+28) – Main register to choose right UART to comunicate, read INT status and adjust INT. Reset by ZX Spectrum Reset
  • Config registerConfig register

    SIFx - Selection of Master or Slave SIF (from rev.02 of Board)
       0 - Master SIF
       1 - Slave SIF
    UARTx – UART selection
       0 - UART 1 – DB9 konektor
       1 - UART 2 – WiFi/Ethernet or IrDA
    INTE – Interrupt Enable
       0 - Disabled
       1 – Interrupt Enabled, automaticaly change to 0 by reading INT Ack
    INTU – Flag for pending Interrupt from ULA.
       0 – No INT pending
       1 – Pending INT from ULA during time between INT Ack and deleting UART1I or UART2I
    UART1I – Interrupt flag from UART1
       0 – No Interrupt
       1 – Pending Interrupt
    UART2I – Interrupt flag from UART2
       0 – No Interrupt
       1 – Pending Interrupt


    This is basic design of device and should be enought for write application. For examples please look to "Software" category.